1. Field of the Invention
The present invention relates to an SOI wafer and also to a method for producing it by transferring a silicon layer from a donor wafer to a carrier wafer.
2. Background Art
SOI wafers (“silicon on insulator”) are generally produced by transferring a silicon layer from a so-called donor wafer to a carrier wafer (“handle wafer” or “base wafer”). Methods for producing SOI wafers by means of the transfer of a silicon layer are known for example by the names Smart Cut® (EP 533551 A1) and Genesis Process®. A further method is described in WO 03/003430A2. SOI wafers comprise a carrier wafer and a silicon covering layer (“top layer” or “device layer”) connected thereto, which represents the so-called active layer that is provided for the production of electronic components. Either the complete carrier wafer is composed of an electrically insulating material such as glass or sapphire, or the silicon covering layer is bonded to the carrier wafer by means of an electrically insulating intermediate layer, for example one composed of silicon oxide. In the latter case, the intermediate layer is referred to as a buried oxide layer “BOX”, and the carrier wafer need not, in this case, be an insulator. By way of example, a semiconductor wafer, preferably a silicon wafer, may be employed as the carrier wafer.
Very high requirements are required of the silicon covering layer. By way of example, the covering layer ought not to have any so-called HF defects. The latter involve “holes” in the covering layer, which may arise inter alia due to the fact that the layer transferred from the donor wafer contains COPs (“crystal originated particles”; vacancy agglomerates) that exceed a critical size. When the covering layer is treated with aqueous hydrofluoric acid solution (HF), the latter can penetrate through the holes to the silicon oxide layer and locally dissolve the latter. The presence of HF defects impairs the function of components produced on the covering layer (A. J. Auberton-Hervé, T. Barge, F. Metral, M. Bruel, B. Aspar, H. Moriceau, THE ELECTROCHEM. SOC. PV98-1 (1998) 1341).
Generally, defect types that are attributable to the presence of point defects, i.e. vacancies or interstitial silicon atoms, and which occur in silicon wafers, are described in the following paragraphs.
Agglomerates of vacancies are referred to, depending on the preparation or detection method, as “Flow Pattern Defects” (FPDs), “Gate Oxide Integrity (GOI) Defects” or “Crystal Originated Particles” (COPs) (D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon, P. Wagner, J. ELECTROCHEM. SOC. 145 (1998) 275).
In the vacancy-rich region in which the vacancies do not agglomerate, oxidation induced stacking faults (OSF) are additionally formed since non-agglomerated vacancies promote oxidization (G. Kissinger, J. Vanhellemont, U. Lambert, D. Gräf, E. Dornberger, H. Richter; J. ELECTROCHEM. SOC. 145 (1998) L75). The formation of the OSF nuclei and also the size of the OSF increase with the oxygen content of the silicon wafer. Therefore, when using vacancy-rich perfect silicon wafers, a low oxygen content is additionally necessary in order to avoid these defects that are harmful to the SOI wafers. In order to achieve this low oxygen content, it is necessary to employ a complicated pulling method, for example using a magnetic field. So-called “perfect silicon” wafers are understood to be wafers which, over substantially their whole area, comprise a so-called neutral region in which point defects (vacancies and/or interstitial silicon atoms) are present but in which agglomeration of point defects does not occur.
Vacancy agglomerates and OSF defects lead to holes in the silicon covering layer of an SOI wafer or to a reduction of the effective layer thickness and thus to a failure of the corresponding components at these locations.
Agglomerates of interstitial silicon atoms lead, in silicon crystals, to dislocation loops having extents of several micrometers (R. Schmolke, W. Angelberger, W. von Ammon, H. Bender, SOLID STATE PHENOMENA VOLS. 82-84 (2002) 231), which likewise adversely affects the function of components produced therefrom.
In order to minimize the problems that arise from the various defects mentioned when producing electronic components on the silicon covering layer of an SOI wafer, epitaxially coated silicon wafers (R. Schmolke, D. Gräf, THE ELECTROCHEM. SOC. PV99-1 (1999) 386) or so-called “perfect silicon wafers” (see U.S. Pat. No. 6,342,725 B2) are generally used as donor wafers. It is known from epitaxially coated wafers, in particular, that such wafers have outstanding material properties with low defect densities. Therefore, epitaxially coated wafers are used for particularly demanding component applications (S. S. Kim, W. Wijaranakula, J. ELECTROCHEM. SOC. 141, (1994) 1872).
The use of epitaxially coated silicon wafers as donor wafers entails the following disadvantages: after the silicon wafer has been transferred to the carrier wafer, the donor wafer is generally reused a number of times in order to enable the SOI wafers to be produced as cost-effectively as possible. If an epitaxially coated silicon wafer is used as a donor wafer, either a very thick epitaxial layer has to be deposited prior to the first use or a new epitaxial deposition has to be carried out again after each use as a donor wafer. Both possibilities are associated with a high outlay and are therefore economically undesirable. Moreover, epitaxially coated silicon wafers have structural defects such as hillocks, spikes and epitaxial stacking faults (F. Passek, R. Schmolke, U. Lambert, G. Puppe, P. Wagner, THE ELECTROCHEM. SOC. PV97-22 (1997) 40), which lead to problems during the bonding of the donor wafer to the carrier wafer.
EP 1170405 A1 and U.S. Pat. No. 6,342,725 B2 describe the use of donor wafers originating from single crystals that have been produced by means of the Czochralski crucible pulling method (referred to hereinafter as the “CZ” method). The parameters of the CZ method are chosen such that the resulting single crystal has a so-called neutral region in which point defects (vacancies or interstitial silicon atoms) are admittedly present, but in which agglomeration of point defects does not occur. Nevertheless, even perfect silicon wafers potentially have small vacancy agglomerates. In order to produce a perfect silicon single crystal that has no agglomerated point defects, it is necessary, during the CZ method, to meet the conditionv/G=(v/G)crit  (1)where v is the pulling speed and G is the axial temperature gradient at the crystallization front. (v/G)crit=1.3×10−3 cm2/(K·min) is a value of this quotient derived from simulation calculations (T. Mori, T. Sinno, R. Brown, THE ELECTROCHEM. SOC. PV99-1 (1999) 425) and confirmed empirically, and has the effect that when it is complied with, no agglomerated point defects are generated, with the result that so-called “perfect” material can be produced. Consequently, only an extremely narrow process window is available during crystal pulling. This narrow process window leads to low yields in the CZ method and, moreover, requires complicated test methods in order to ensure that the crystal quality corresponds to the requirements needed. In this case, there is furthermore a strong tendency for at least the radial defect behavior to be inhomogeneous. This means that both vacancy-rich regions (with potential OSF defects) and regions with interstitial silicon atoms occur simultaneously in a silicon wafer.
Another approach for keeping the defects in donor wafers as small as possible and reducing defect densities consists in using vacancy-rich crystals with nitrogen as a co-dopant (D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon, P. Wagner, THE ELECTROCHEM. SOC. PROC. Vol. 96-13 (1996) 117). As a result of co-doping with nitrogen, it is possible to suppress vacancy agglomerates (“voids”) present in vacancy-rich crystals during growth and thus to reduce the harmful influence on the SOI structures (EP 969505 A2). However, even small vacancy agglomerates lead to adverse effects on SOI structures, particularly if the thickness of the silicon covering layer lies in the region of 100 nm or less. This is primarily the case with SOI wafers that are provided for the production of so-called “partially depleted,” and in particular, “fully depleted” SOI structures.